Currently produced complementary-metal-oxide-semiconductor (CMOS) devices, e.g., 20 nm and above, include FinFETs which are generally formed on silicon on insulator (SOI) or bulk substrates. A SOI FinFET may provide better isolation between the source and drain, as well as less junction leakage. The smaller parasite capacitance of the SOI FinFET also provides stronger AC performance and there is no need for shallow trench isolation (STI). However, a SOI substrate is more expensive than a bulk substrate. Alternatively a bulk FinFET has stronger strain engineering for enhancement of channel mobility and is better compatible with planar CMOS process flow. Although bulk FinFETs need halo implants for isolation between source and drain regions. In addition, bulk FinFET devices experience more junction leakage and gate-induced drain leakage (GIDL) than SOI substrates. Bulk substrates also have larger parasite junction capacitance which degrades AC performance.
Thus, the fabrication of FinFET devices can be problematic with existing substrates and designs and improved substrates and FinFET device designs are needed for forming FinFET devices to improve the electrical performance of the resultant semiconductor devices.